Video: Charting the Future of AI/ML with Open Standards and Global Collaboration
Phil Tomi, Technical Steering Committee Vice Chair, discusses RISC-V’s critical role in AI development, highlighting its flexibility for custom silicon design, strong ecosystem support, and emerging standards that enable efficient, domain-specific acceleration for AI applications, positioning RISC-V as the preferred architecture for building AI accelerators
Common Language for the Development of AI Systems
A New Standard For AI
RISC-V is quickly becoming the preferred standard for building performant and efficient AI accelerators, bringing together experts from different geographies and
industries to define the AI solutions of tomorrow.
A Common Language For AI
RISC-V provides a common language for AI development, as an industry standard ISA, backed by a cohesive ecosystem for AI/ML development addressing all market segments.
Ecosystem Support
A unified ecosystem unites global experts across industries to define tomorrow’s AI solutions, delivering innovative technologies for future generations.
Software-Based Approach to Hardware
Software Focused
The extensible industry standard RISC-V ISA enables a software-focused approach to AI hardware, and a unified programming model across AI workloads running on CPU, GPU & NPU
Workload-Based Customization
RISC-V’s modular architecture enables industry leading differentiation, through the development of custom instructions and accelerators targeted at your software work–load
Future Proofed
The latest advancements in AI/ML algorithms can be quickly integrated into hardware designs, keeping pace with fast-evolving demands.
Control your Compute Roadmap & Supply Chain
Tailored Customization
RISC-V allows for domain-specific customization tailored to particular applications and workloads by enabling the selection of appropriate ratified extensions from the standard.
Extensibility
RISC-V enables the addition of ratified extensions from the standard or vendor-
developed extensions to differentiate products with application-specific functionality.
Freedom to Innovate
A standardized yet flexible platform allows designers to rapidly integrate cutting-edge research into hardware without being hampered by proprietary constraints.
Building a Better Business Case for AI
Cost Efficient
RISC-V enables rapid innovation and cost-effective development.
No Lock-In
Free from restrictions of vendor lock-in RISC-V enables open collaboration and pooled resources to advance one interoperable global standard.
Flexibility
By reducing barriers to entry and democratizing AI, RISC-V is a standardized yet
flexible foundation that upends the economics of custom silicon x enabling industry-leading differentiation.
Hear from our Members About RISC-V and AI
LLM Inference on RISC-V Embedded CPUs
Yueh-Feng Lee, Andes Technology
The Future of AI and Security
Andrew Dellow, Qualcomm; Kris Murphy, NVIDIA; Pete Bernard, tinyML Foundation; Pete Warden, Useful Sensors Inc; Andrea Gallo, RISC-V International
Lessons Learned in Using RISC-V for Generative AI and Where We Can Go from Here
Jayesh Iyer & Josep M Perez, Esperanto Technologies
Building Tool Chains for RISC-V AI Accelerators
Jeremy Bennett, Embecosm
The Benefits of Building New AI Accelerators with RISC-V
Cliff Young & Martin Maas, Google DeepMind
RISC-V at NVIDIA: One Architecture, Dozens of Applications, Billions of Processors
Frans Sijstermans, Vice President Multimedia Arch/ASIC, NVIDIA
All-in-One RISC-V AI Compute Engine
Roger Espasa, Semidynamics
Bring Your Code to RISC-V Accelerators With SYCL
Charles Macfarlane, Codeplay
Use of RISC-V as Multiprocessor Host With In Memory Computing
Carmine Cappetta, STMicroelectronics
Panel Discussion: Accelerating AI Innovation with RISC-V
Explore the Latest RISC-V AI Content
May 20, 2025
Today’s system-on-chip (SoC) designs integrate unprecedented numbers of diverse IP cores, from general-purpose CPUs to specialized hardware accelerators, including neural processing units (NPUs), tensor processors, and data processing units (DPUs). This heterogeneous approach enables designers…
May 15, 2025
In just two years, Semidynamics has “evolved from RISC-V with AI to AI with RISC-V”, Semidynamics’ chief sales officer Volker Politz said at this week’s RISC Summit Europe 2025 in Paris. In 2023, the Barcelona,…
May 14, 2025
Flow Computing in Finland has started alpha testing of a RISC-V compiler for its Parallel Processing Unit (PPU) AI block. The PPU is capable of increasing any CPU architecture by up to 100X by using the compiler…
May 14, 2025
Laguna Hills, California. BrainChip Holdings Ltd released information it is now integrating Andes Technology’s RISC-V cores with its NPUs. According to the press release, the companies will exhibit BrainChip’s Akida AKD1500 on Andes’ QiLai Voyager Board and AndesCore AX45MP…
May 7, 2025
Laguna Hills, California. BrainChip Holdings Ltd released information it is now integrating Andes Technology’s RISC-V cores with its NPUs. According to the press release, the companies will exhibit BrainChip’s Akida AKD1500 on Andes’ QiLai Voyager Board and AndesCore AX45MP…
May 7, 2025
Semidynamics has introduced Cervell™, a highly scalable and fully programmable Neural Processing Unit (NPU) architected on RISC-V. Cervell seamlessly merges CPU, vector, and tensor capabilities within a unified, all-in-one architecture, enabling zero-latency AI computation across a…